Silicon on insulator transistor structure for imbedded DRAM

ABSTRACT

To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present invention is related to that disclosed in Serial No. 60/115,843 [Atty. Docket No. CHOI 5-50-70], filed on Jan. 13, 1999, entitled “SOI-BASED TR. STRUCTURE FOR EDRAM” and commonly assigned with the present invention.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention is directed, in general, to integrated circuit fabrication and, more specifically, to high-density DRAM applications in which the transistor device has a lowered transistor Ioff and a method of manufacture thereof.

BACKGROUND OF THE INVENTION

[0003] As is well known, dynamic random access memories (DRAMs) are so named because their cells can retain information only temporarily even with power continuously applied. The cells must therefore be read and refreshed at periodic intervals. Storage time is long enough to allow for many memory operations between refresh cycles. The advantages of cost per bit, device density, and flexibility of use have made DRAMs a widely used form of semiconductor memory.

[0004] The use of DRAM devices in integrated circuit designs has grown extensively over the years. Likewise, the density of the number of DRAM devices within certain integrated circuits has also increased substantially over the last few years. As device sizes have decreased, this has allowed manufacturers to increase the DRAM density even more. Along with the increase use of DRAM devices, however, a number of problems arose.

[0005] One such problem was the parasitic effect associated with operation of the DRAM device. Because of the smaller device size and the high operating currents due to large size of DRAM array, eddy currents would form within the P substrate. These eddy currents were highly undesirable because they caused the device to be inefficient. Furthermore, the eddy currents increased operating temperatures, which shortened the useful life of the device. To address this problem, manufactures inserted a buried oxide, which is often referred to as silicon on insulator (SOI). The SOI layer isolated the P-tub or N-tub from the substrate and thereby decreased the parasitic effect.

[0006] Although it has been found that the SOI somewhat decreases Ioff with some degree of success, the Ioff needs to be further reduced for the DRAM application. This high Ioff requirement in DRAMs can cause many problems related to heat transfer and hot carrier effects as well as more heat dissipation. Moreover, DRAMS are more temperature sensitive, and the increased temperature that accompanies larger current flows can damage the integrated circuit in which the DRAM device is located. Furthermore, a higher transistor Ioff can also lead to reduce the data storage time. This requires more frequent refresh-cycle time, resulting in a large power consumption.

[0007] There have been many attempts to reduce this excessively high Ioff. One such attempt calls for constructing a transistor without an n+ source and drain region. However, devices of this type are undesirable since they require a narrow process margin and additional masks. Moreover, leakage and degradation of transistor Ion may result. Another attempt has been to dope the SOI with n-type dopants. However, this has produced undesirable results in that the dopants caused leakage within the active layer. While these attempts have been directed to a lower transistor Ioff, this result is not always guaranteed. Many of the mentioned problems could be solved if a lower transistor Ioff in DRAMS is guaranteed.

[0008] Accordingly, what is needed in the art is a DRAM transistor that can be reliably manufactured, and a DRAM transistor that requires a lower transistor Ioff under a wide variety of process conditions. The present invention addresses this need.

SUMMARY OF THE INVENTION

[0009] To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, including a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer. The ultra thin active layer includes a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. Thicknesses of conventional active layers typically range from about 600 nm to about 800 nm, such that a low Ioff ranging from about 10⁻¹¹ to about 10⁻¹² can be achieved.

[0010] The ultra thin active layer employed in the present invention is substantially thinner than these conventional active layers. For example, in one particularly advantageous embodiment, the ultra thin active layer in the integrated circuit may have a thickness ranging from about 25 nm to about 10 nm with one preferably thickness being approximately 15 nm. However, other thicknesses of the ultra thin active layer may range from about 45 nm to about 30 nm.

[0011] The present invention therefore introduces the broad concept of an integrated circuit having a DRAM with an ultra thin active layer formed on a SOI layer in which a low Ioff can be achieved.

[0012] In one embodiment, the ultra thin active layer is doped with a P-type dopant and the source and drain regions are doped with an N-type dopant.

[0013] In one embodiment, the ultra thin active layer forms an active layer of a dynamic random access memory (DRAM) device. In one aspect of this particular embodiment, the DRAM device is a high density DRAM device.

[0014] In another embodiment, the insulator is a dielectric material such as silicon dioxide and has a thickness of at least about 0.5 μm. In yet another embodiment, the base substrate is a heavily doped substrate having a dopant concentration of at least about 10¹⁷ atoms/cm³.

[0015] In yet another embodiment, the present invention discloses a method of fabricating an integrated circuit located on a semiconductor wafer, including: forming doped base substrate; forming an insulator layer over the doped base substrate; and forming a doped ultra thin active layer on the insulator layer. The ultra thin active layer includes a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate.

[0016] In yet another embodiment, the present invention discloses a high density dynamic random access memory (DRAM) device formed on a semiconductor wafer, including; a plurality of transistors; and a plurality of DRAM transistors, at least one of the DRAM transistors electrically connected to at least one of the plurality of transistors and at least one of the DRAM transistors including: a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer. The ultra thin active layer includes a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate.

[0017] The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0019]FIG. 1 illustrates a partial sectional view of a DRAM device in the prior art after the formation of gates and spacers;

[0020]FIG. 2 illustrates a partial sectional view of the present invention's buried oxide layer and the present invention's ultra thin active layer; and

[0021]FIG. 3 illustrates a partial sectional view of the present invention after the formation of source and drain, gates and spacers.

DETAILED DESCRIPTION

[0022] Referring initially to FIG. 1, there is illustrated a partial sectional view of a semiconductor device 100 of the prior art. Semiconductor device 100 may contain a P substrate 101, a buried oxide layer 102 and an active region 103. Furthermore, semiconductor device 100 may contain a gate oxide 104, a gate 105, and an oxide spacer 106. The active region in a conventional semiconductor device ranges from about 60 nm to about 200 nm.

[0023] It is believed that the thickness of the active region induces an unreasonably high transistor Ioff in a semiconductor device. A high transistor Ioff in semiconductor devices causes many problems related to heat transfer and hot carrier effects as well as high heat dissipation. Furthermore, a higher transistor Ioff in semiconductor devices make the devices more temperature sensitive. More importantly, a higher transistor Ioff can lead to the inability to distinguish the “on” state from the “off” state when minimal bits are employed. Overall, a high transistor Ioff requires more power to operate conventional DRAMs and induces undesirable power-related effects within the semiconductor device.

[0024] The present invention calls for ultra thinning the active layer region in order to lower the transistor Ioff. A suggested explanation why the transistor Ioff decreases is that the active P-tub region is more easily depleted by the gate oxide and the buried oxide layer(silicon on insulator). Because the P-tub region is more easily depleted, leakage current is less likely to occur; therefore, less leakage current is added to the Ioff. Consequently, a lower Ioff is achieved in the device, and a lower standby current is achieved in the circuit. The present invention, therefore, provides a lower Ioff with reasonably good ion characteristics.

[0025] In reference to FIG. 2, there is illustrated a partial sectional view of a semiconductor device 200 of the present invention in an intermediate fabrication step. In this particular embodiment, the semiconductor device 200 comprises a heavily doped P substrate layer 201 (e.g., a dopant concentration of at least about 10¹⁷ atoms/cm³) , a buried oxide layer 202 and an ultra thin active layer 203, respectively, formed thereon in a conventional manner. While p-type dopants are specifically discussed herein, it should be understood that other dopant types may also be used. For example, the substrate may be a heavily doped N substrate. The substrate may comprise silicon, germanium, or other presently known or later-discovered materials that are suitable for the manufacture of such semiconductor devices.

[0026] In one advantageous embodiment, the buried oxide layer 202, which is an insulator formed with a dielectric material such as silicon dioxide. Preferably, the buried oxide layer 202 is a good quality oxide having has a thickness that ranges from about 0.25 μm to about 1.0 μm. A more preferred thickness is at least about 0.5 μm. The substrate is preferably a heavily doped substrate having a dopant concentration of at least about 10¹⁷ atoms/cm³.

[0027] In one advantageous embodiment, the ultra thin active layer 203 has a thickness ranging from about 10 nm to about 25 nm, which is deposited by conventional processes. A preferable thickness of the active layer 203 is approximately 15 nm. The active layer may comprise silicon, germanium, or other presently known or later-discovered materials that are suitable for the active layer. It is believed that by thinning the active layer 203, there are collectively fewer electron holes within the active layer 203; thus, the active layer 203 more easily depleted by the buried oxide layer 202. Because the active layer 203 is more depleted, the active layer 203 does not have an abundance of charge. Therefore, tunneling from the source to the drain 307 within the P-tub region 203 is substantially inhibited and current is not significantly added to the transistor Ioff. In a more advantageous embodiment, the ultra thin active layer 203 forms an active layer of a dynamic random access memory (DRAM) device. such as a high density DRAM device. In one such device, the ultra thin active layer 203 is doped with a P-type dopant and the source and drain regions are doped with an N-type dopant. Given the similar structures between the NMOS and the semiconductor devices covered by the present invention, it is apparent that the same results could be expected in semiconductor devices as appears in the NMOS devices, as well as CMOS Ioff.

[0028]FIG. 3 illustrates a partial sectional view of a semiconductor device 300 of the present invention after the formation of a doped base substrate 201, an insulator layer 302 formed over the doped base substrate 201, and a doped ultra thin active layer 203 formed on the insulator layer 202. The ultra thin active layer 203 includes a gate oxide 304, a gate 305 formed on the gate oxide 304, and source and drain regions 307 formed in the ultra thin active layer 203 and adjacent the gate 305. The source and drain region 307, the gate oxide 304, a gate 305, and the oxide spacer 306 are formed by conventional means. Note that the figures illustrated are only partial sectional views of a semiconductor device, and one skilled in the art recognizes that the structure of a semiconductor device varies considerably.

[0029] Also illustrated in FIG. 3 is a polysilicon structure that has been deposited, doped and etched using conventional processes to form a gate 305. The gate 305 is formed over a gate oxide 304. The semiconductor structure 300 may also include spacers 306 or gate side-walls that are formed around the gate 305. The process of forming the spacers 306 are well known. The substrate 301, buried oxide layer 202, P-tub region 203, gate 305, gate oxide 304 and spacers 306 provide the resulting structure that is representative of a foundational level of semiconductor structures having a significantly lower Ioff.

[0030] Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form. 

What is claimed is:
 1. An integrated circuit formed on a semiconductor wafer, comprising: a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate.
 2. The integrated circuit as recited in claim 1 wherein the ultra thin active layer has a thickness ranging from about 10 nm to about 25 nm.
 3. The integrated circuit as recited in claim 1 wherein the ultra thin active layer forms an active layer of a dynamic random access memory (DRAM) device.
 4. The integrated circuit as recited in claim 3 wherein the DRAM device is a high density DRAM device.
 5. The integrated circuit as recited in claim 1 wherein the ultra thin active layer is doped with a P-type dopant and the source and drain regions are doped with an N-type dopant.
 6. The integrated circuit as recited in claim 1 wherein the insulator is silicon dioxide and has a thickness of at least about 0.5 μm.
 7. The integrated circuit as recited in claim 1 wherein the base substrate is a heavily doped substrate having a dopant concentration of at least about 10¹⁷ atoms/cm³.
 8. A high density dynamic random access memory (DRAM) device formed on a semiconductor wafer, comprising; a plurality of transistors; and a plurality of DRAM transistors, at least one of the DRAM transistors electrically connected to at least one of the plurality of transistors and at least one of the DRAM transistors including: a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate.
 9. The high density DRAM device as recited in claim 8 wherein the ultra thin active layer has a thickness ranging from about 25 nm to about 10 nm.
 10. The high density DRAM device as recited in claim 8 wherein the plurality of transistors includes at least one complementary metal oxide semiconductor (CMOS) transistor.
 11. The high density DRAM device as recited in claim 8 wherein the ultra thin active layer is doped with an N-type dopant and the source and drain regions are doped with a P-type dopant.
 12. The high density DRAM device as recited in claim 8 wherein the ultra thin active layer is doped with a P-type dopant and the source and drain regions are doped with an N-type dopant.
 13. The high density DRAM device as recited in claim 8 wherein the insulator is silicon dioxide and has a thickness of at least about 0.5 μm.
 14. The high density DRAM device as recited in claim 8 wherein the base substrate is a heavily doped substrate having a dopant concentration of at least about 10¹⁷ atoms/cm³.
 15. A method of fabricating an integrated circuit located on a semiconductor wafer, comprising: forming doped base substrate; forming an insulator layer over the doped base substrate; and forming a doped ultra thin active layer on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate.
 16. The method as recited in claim 15 wherein forming a doped ultra thin active layer includes forming the ultra thin active layer to a thickness ranging from about 25 nm to about 10 nm.
 17. The method as recited in claim 15 wherein forming an ultra thin active layer includes forming an active layer of a dynamic random access memory (DRAM) device.
 18. The method as recited in claim 17 wherein forming an active layer of a DRAM device includes forming a high density DRAM device.
 19. The method as recited in claim 15 wherein forming an ultra thin active layer includes doping the ultra thin active layer with a P-type dopant and doping the source and drain regions with an N-type dopant.
 20. The method as recited in claim 15 wherein forming an insulator includes forming a silicon dioxide layer to a thickness of at least about 0.5 μm.
 21. The method as recited in claim 15 wherein forming a base substrate includes forming a heavily doped substrate having a dopant concentration of at least about 10¹⁷ atoms/cm³. 